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LOW SKEW, 1-TO-9 DIFFERENTIAL-TOLVCMOS ZERO DELAY BUFFER
ICS87951I-147
GENERAL DESCRIPTION
The ICS87951I-147 is a low voltage, low skew 1IC S to-9 Differential-to-LVCMOS/LVTTL Zero Delay HiPerClockSTM Buffer and a member of the HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS87951I-147 has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the ICS87951I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87951I147 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".
FEATURES
* Fully integrated PLL * Nine single ended 3.3V or 2.5V LVCMOS/LVTTL outputs * Selectable single ended CLK0 or differential CLK1, nCLK1 inputs * The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels * CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Output frequency range: 31.25MHz to 200MHz * VCO range: 250MHz to 500MHz * External feedback for "zero delay" clock regeneration * Cycle-to-cycle jitter, RMS: 7ps (maximum) * Output skew: 270ps (maximum) * Full 3.3V operating supply at -40C to 85C ambient operating temperature * Full 2.5V operating supply at 0C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
PIN ASSIGNMENT
CLK_SEL PLL_SEL CLK0 GND GND VDDO QA QB
32 31 30 29 28 27 26 25 VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
nCLK1 MR/nOE VDDO QD4 GND QD3 VDDO QD2
24 23 22
QC0 VDDO QC1 GND QD0 VDDO QD1 GND
ICS87951I-147
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
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BLOCK DIAGRAM
DIV_SELA Internal Pulldown PLL_SEL Internal Pulldown CLK0 Internal Pulldown CLK_SEL
Internal Pulldown
nCLK1 CLK1
Internal Pulldown/ Pullup
1 0 PHASE DETECTOR VCO 250-500MHz 0 1
/2 /4 /8
0
QA
1
0 LPF 1
EXT_FB Internal Pullup DIV_SELB Internal Pulldown QB
0 1
QC0 QC1
DIV_SELC Internal Pulldown MR/nOE Internal Pulldown
POWER-ON RESET 0 1
DIV_SELD Internal Pulldown
QD0 QD1 QD2 QD3 QD4
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7, 13, 17, 21, 25, 29 8 9 10 11, 15, 19, 23, 27 12, 14, 16, 18, 20 22, 24 26 28 30 31 32 Name VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 nCLK1 MR/nOE Power Input Input Input Input Input Power Input Input Input Pullup Pullup Pulldown Pulldown Pulldown Pulldown Type Description Analog supply pin. Feedback input to phase detector for regenerating clocks with "zero delay". LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank C outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank D outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Power supply ground. Non-inver ting differential clock input.
Pulldown Inver ting differential clock input. Active High Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated Pulldown (HiZ). When logic LOW, the internal dividers and outputs are enabled. LVCMOS / LVTTL interface levels. Output supply pins. Bank D clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7 typical output impedance. LVCMOS / LVTTL interface levels. Bank B clock output. 7 typical output impedance. LVCMOS / LVTTL interface levels. Bank A clock output. 7 typical output impedance. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL phase detector reference clock input. Selects between the PLL and the reference clock as the input to the Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK0. When LOW, Pulldown selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
VDDO QD4, QD3, QD2, QD1, QD0 QC1, QC0 QB QA CLK0 PLL_SEL CLK_SEL
Power Output Output Output Output Input Input Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor VDDA, VDDO = 3.465V VDDA, VDDO = 2.625V Test Conditions Minimum Typical 4 25 15 51 51 Maximum Units pF pF pF k k
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TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Input MR/nOE 1 0 QA HiZ Enabled QB HiZ Enabled Outputs QC0, QC1 HiZ Enabled QD0:QD4 HiZ Enabled
TABLE 3B. OPERATING MODE FUNCTION TABLE
Input PLL_SEL 0 1 Operating Mode Bypass PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs CLK_SEL 0 1 PLL Input CLK1, nCLK1 CLK0
TABLE 3D. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs DIV_SELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DIV_SELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DIV_SELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIV_SELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 QB VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 Outputs QCx VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 QDx VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDDA + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 42.1C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDDA VDDO IDDO IDDA Parameter Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current All VDD pins Test Conditions Minimum 3.135 3.135 Typical 3.3 3. 3 Maximum 3.465 3.465 115 20 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 2.5V5%, TA = 0C TO 85C
Symbol VDDA VDDO IDDO IDDA Parameter Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current All VDD pins Test Conditions Minimum 2.375 2.375 Typical 2. 5 2.5 Maximum 2.625 2.625 75 12 Units V V mA mA
TABLE 4C. DC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH Input High Voltage DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL CLK0 Test Conditions Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL IIN VPP VCMR VOH VOL
Input Low Voltage
-0.3 -0.3
0.8 1.3 120
V V A V V V
Input Current Peak-to-Peak CLK1, nCLK1 Input Voltage Common Mode Input Voltage; CLK1, nCLK1 NOTE 1, 2 Output High Voltage Output Low Voltage
0.15 GND + 0.5 IOH = -40mA IOL = 40mA IOL = 12mA 2.4
1.3 VDD - 0.85
0.55 0.3
V V
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is VDDA+ 0.3V.
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TABLE 4D. DC CHARACTERISTICS, VDDA = VDDO = 2.5V5%, TA = 0C TO 85C
Symbol Parameter VIH Input High Voltage DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL DIV_SELA:DIV_SELD, EXT_FB, MR/nOE, PLL_SEL, CLK_SEL CLK0 Test Conditions Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL IIN VPP VCMR VOH VOL
Input Low Voltage
-0.3 -0.3
0.8 0.8 150
V V A V V V
Input Current Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage Output Low Voltage
CLK1, nCLK1 CLK1, nCLK1 IOH = -15mA IOL = 15mA
0.15 GND + 0.5 1.8
1.3 VDD - 0.85
0.6
V
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is VDDA+ 0.3V.
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fREF Parameter Input Reference Frequency Test Conditions Minimum Typical Maximum 250 Units MHz
TABLE 6A. AC CHARACTERISTICS, VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fMAX fVCO t(O) Parameter Output Frequency PLL VCO Lock Range CLK0 Static Phase Offset; CLK1, NOTE 1,3 nCLK1 Output Skew; NOTE 2, 3 Cycle-to-Cycle Jitter, RMS; NOTE 3 PLL Lock Time; NOTE 3 Output Rise/Fall Time Output Duty Cycle Output Enable Time Output Disable Time fREF = 50MHz, Feedback = VCO/8 Test Conditions QA /2 Qx /4 QB, QC, QD /8 250 -135 -420 Minimum Typical Maximum 250 125 62.5 500 170 -100 270 All Outputs @ Same Frequency 7.5 10 20% to 80% 30 0 46 800 54 6 7 Units MHz MHz MHz MHz ps ps ps ps mS ps % ns ns
tsk(o) tjit(cc)
tLOCK tR / tF odc tPZL tPLZ, tPHZ
All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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TABLE 6B. AC CHARACTERISTICS, VDDA = VDDO = 2.5V5%, TA = 0C TO 85C
Symbol fMAX fVCO t(O) Parameter Output Frequency PLL VCO Lock Range CLK0 Static Phase Offset; CLK1, NOTE 1,3 nCLK1 Output Skew; NOTE 2, 3 Cycle-to-Cycle Jitter, RMS; NOTE 3 PLL Lock Time; NOTE 3 Output Rise/Fall Time Output Duty Cycle Output Enable Time Output Disable Time Test Conditions QA /2 Qx /4 QB, QC, QD /8 250 -180 -500 FVCO 400MHz, All Outputs @ same frequency 20% to 80% 300 46 Minimum Typical Maximum 200 120 60 500 220 -165 310 9 10 700 54 6 7 Units MHz MHz MH z MHz ps ps ps ps mS ps % ns ns
tsk(o) tjit(cc)
tLOCK tR / tF o dc tPZL tPLZ, tPHZ
All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDDA, VDDO
SCOPE
Qx
VDDA, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DDO
nCLK1
Qx
2
V
CLK1
PP
Cross Points
V
CMR
V
DDO
Qy
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
QA, QB, QCx, QDx V V V
OUTPUT SKEW
DDO
DDO
DDO
2
2
2
80% 20% tR
80% 20% tF
tcycle n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
QAx, QBx, QCx, QDx
t PW
t
PERIOD
t(O)
odc =
t PW t PERIOD
tjit(O) = t(O) -- t(O) mean = Phase Jitter
x 100%
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PHASE JITTER AND STATIC PHASE OFFSET
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V
DDO
tcycle n+1
Clock Outputs
OUTPUT RISE/FALL TIME
nCLK1 CLK0, CLK1
2
VDD
EXT_FB
2
t(O) mean = Static Phase Offset
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87951I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DDA, and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V VDDO .01F VDDA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVCMOS OUTPUT: All unused LVCMOS output can be left floating. There should be no trace attached.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V
3.3V 1.8V
3.3V Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 HiPerClockS Input
LVPECL R1 50 R2 50 Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
R3 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V LVDS_Driv er
Zo = 50 Ohm
CLK R1 100 Zo = 50 Ohm
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87951I-147 is: 2674 Pin compatible with the MPC951
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PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS87951AYI-147 ICS87951AYI-147T ICS87951AYI-147LF ICS87951AYI-147LFT Marking ICS87951AYI-147 ICS87951AYI-147 ICS951AI147L ICS951AI147L Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev A A Table T9 T9 Page 1 13 10 13 Description of Change Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free par t number and note. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected standard marking and added lead-free marking. Date 6/14/05 6/21/06
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